Stacked packages

ABSTRACT

A stacked chip assembly includes individual units having chips mounted on dielectric layers and traces on the dielectric layers interconnecting the contacts of the chips with terminals disposed in peripheral regions of the dielectric layers. At least some of the traces are multi-branched traces which connect chip select contacts to chip select terminals. The units are stacked one above the other with corresponding terminals of the different units being connected to one another by solder balls or other conductive elements so as to form vertical buses. Prior to stacking, the multi-branched traces of the individual units are selectively connected, as by forming solder bridges, so as to leave chip select contacts of chips in different units connected to different chip select terminals and thereby connect these chips to different vertical buses. The individual units desirably are thin and directly abut one another so as to provide a low-height assembly with good heat transfer from chips within the stack.

CROSS-REFERENCE TO RELATED APPLICATIONS

This application is divisional application of U.S. patent applicationSer. No. 10/454,029, filed Jun. 4, 2003, which application is acontinuation-in-part of U.S. patent application Ser. No. 10/267,450,filed Oct. 9, 2002, now U.S. Pat. No. 6,897,565, which in turn claimsbenefit of the filing date of U.S. Provisional Patent Application Ser.No. 60/328,038 filed Oct. 9, 2001. The disclosures of the aforementionedapplications are hereby incorporated by reference herein.

BACKGROUND OF THE INVENTION

The present application relates to microelectronic assemblies and, inparticular, to stacked packages, and to components and methods useful inmaking such assemblies.

Semiconductor chips typically are thin and flat, with relatively largefront and rear surfaces and small edge surfaces. The chips have contactson their front surfaces. Typically, chips are provided as packaged chipshaving terminals suitable for connection to an external circuit.Packaged chips typically are also in the form of flat bodies.Ordinarily, the packaged chips are arranged in an array on a surface ofa circuit board. The circuit board has electrical conductors, normallyreferred to as “traces” extending in horizontal directions parallel tothe surface of the circuit board and also has contact pads or otherelectrically conductive elements connected to the traces. The packagedchips are mounted with their terminal-bearing faces confronting thesurface of the circuit board and the terminals on each packaged chip areelectrically connected to the contact pads of the circuit board.

Memory chips typically are mounted in this manner. An unpackaged memorychip typically has numerous data contacts and one or a few selectcontacts. The chip is arranged to ignore data or commands appearing atthe data terminals unless the appropriate signals are applied to theselect contact or contacts. A conventional packaged memory chip has dataterminals connected to the data contacts and has select terminalsconnected to the select contacts. In a conventional system, numerousidentical packaged memory chips can be connected in an array with thecorresponding data terminals of the various packaged chips connected tocommon traces and with the select terminals of the various chipsconnected to unique conductors, so that each conductor is associatedwith one, and only one, chip. Data can be written onto an individualchip by supplying the data on the common traces and by applying aselection signal on the unique trace associated with the particular chipwhere the data is to be written. The remaining chips will ignore thedata. The reverse process is employed to read data from a particularchip. Such a circuit can be built readily using the conventionalhorizontal chip array and using identical chip packages for all of thechips in the array.

In the conventional arrangement, the theoretical minimum area of thecircuit board is equal to the aggregate areas of all of theterminal-bearing surfaces of the individual chip packages. In practice,the circuit board must be somewhat larger than this theoretical minimum.The traces on the circuit board typically have significant length andimpedance so that appreciable time is required for propagation ofsignals along the traces. This limits the speed of operation of thecircuit.

Various approaches have been proposed for alleviating these drawbacks.One such approach is to “stack” plural chips one above the other in acommon package. The package itself has vertically-extending conductorsthat are connected to the contact pads of the circuit board. Theindividual chips within the package are connected to thesevertically-extending conductors. Because the thickness of a chip issubstantially smaller than its horizontal dimensions, the internalconductors can be shorter than the traces on a circuit board that wouldbe required to connect the same number of chips in a conventionalarrangement. Examples of stacked packages are shown, for example, inU.S. Pat. Nos. 5,861,666; 5,198,888; 4,956,694; 6,072,233; and6,268,649. The stacked packages shown in certain embodiments of thesepatents are made by providing individual units, each including a singlechip and a package element having unit terminals. Within each unit, thecontacts of the chip are connected to the unit terminals. The units arestacked one atop the other. Unit terminals of each unit are connected tothe corresponding unit terminals of other units. The connected unitterminals form vertical conductors of the stacked package, also referredto as buses.

However, providing a circuit with individual select connections in astacked package introduces additional complexities. Because the verticalconductors extend through the terminals of the various units, theinterconnections between the contacts of the chip and the unit terminalsof each unit in the stack should be different in order to provideconnections to unique vertical conductors. For example, in a four-chipstack having four vertical buses for carrying selection signals, thebottom unit may have a select contact of its chip connected to a unitterminal that forms part of bus number 1; the next unit may have acorresponding select contact of its chip connected to a terminal thatforms bus number 2; and so on. This need for customization of the unitsadds complexity to the manufacturing process. For example, U.S. Pat. No.4,956,694 describes units having chip carriers with a set ofintermediate terminals in each unit. These intermediate terminals areconnected to the contacts on the chip and are also connected to theterminals of the unit. The interconnections are made by wire bonds. Thepattern of wire bonds differs from unit to unit. This arrangementinherently requires a relatively large chip carrier, which adds to thecost and bulk of the package. Moreover, the manufacturer must handle andstock multiple different wire bonded units. Sugano et al., U.S. Pat. No.5,198,888, uses individualized chip carriers in the various units. Thesechip carriers have leads defining different interconnect patterns forthe select contacts and the associated terminals. This, again, adds tothe cost and complexity of the manufacturing process. U.S. Pat. Nos.6,268,649 and 6,072,233 use customized units as well. It would bedesirable to reduce the cost and complexity associated with providingcustomized units in a stacked package.

It would also be desirable to provide a compact stacked package and toprovide a stacked package with good heat transfer from the chips withinthe stack to the external environment as, for example, to the circuitboard or to a heat spreader overlying the top of the package. Further,it would be desirable to provide such a package using readily-availableequipment and using components that can be fabricated readily.

In addition, it would be desirable to provide a stacked package thatmitigates signal noise and distortion. As such, it would also bedesirable to shield other components external to the stacked packagefrom electromagnetic radiation emanating from the stacked package.Likewise, it would also be desirable to shield the chips, or devices, ofa stacked package from external electromagnetic radiation impingingthereon.

SUMMARY OF THE INVENTION

One aspect of the invention provides semiconductor chip assembliesincorporating a plurality of units. Each unit desirably includes asemiconductor chip having at least one select contact and a plurality ofother contacts and also includes a circuit panel having a plurality ofchip select terminals and a plurality of other terminals, as well astraces extending on or in the panel. The traces are electricallyconnected between the contacts of the chip and the terminals. The traceelectrically connected to each chip select contact of the chip desirablyis a multi-branched trace including a common section connected to theselect contact of the chip and also including a plurality of branchesconnected to different ones of the chip select terminals on the circuitpanel. In the assembly, desirably at least one branch, but less than allof the branches of each such multi-branch trace, have an interruptiontherein so that the select contact is connected to less than all of thechip select terminals on the panel and most preferably so that each chipselect contact is connected to only one chip select terminal of thepanel in the unit. The units are disposed one above the other in a stackof superposed units. The assembly further includes vertical conductors,each connecting the corresponding terminals of the units in the stack toone another so as to form a plurality of vertical buses. Due to theselective connections within individual units provided by themulti-branch traces and interrupted branches, the chip select contactsof chips in different units are electrically connected to different onesof the vertical buses. This arrangement provides selective routing ofchip select signals and other signals which must be conveyed toindividual chips. The remaining contacts on each chip are connected inparallel with corresponding contacts on chips in other units so thatsignals can be conveyed to the remaining contacts of the various chipsin parallel. This provides the required selective routing.

Most preferably, the chips, traces and terminals of different units inthe stack are identical to one another, except that different ones ofthe units have different branches of their multi-branch tracesinterrupted so that different chip select contacts of different unitsare connected to different terminals on the circuit panels of suchunits. Most preferably, the circuit panel of each unit includes adielectric layer, desirably less than about 100 μm thick. The verticalspacing distance between corresponding features in adjacent ones of theunits desirably is no more than about 250 μm and preferably no more thanabout 200 μm greater than the thickness of the chip in each unit. Theassembly, thus, has a relatively low overall height.

The dielectric layer in each circuit panel may have a disconnectionaperture or opening, and the interruptions in the branches of themulti-branch traces may be formed at such disconnection apertures. Thedisconnection apertures can be formed in the dielectric layers when theunits are manufactured or when the branches are interrupted, typicallyat a later stage in the process. In one arrangement, the circuit panelof each unit has edges, and the disconnection apertures are provided inthe form of notches extending inwardly from one or more of the edges.The terminals of such a unit may include an outer row disposed adjacentto an edge of the circuit panel and the branches of the multi-branchtraces may have portions extending outwardly to or beyond the outer rowof terminals. In this instance, the notches need not extend inwardlybeyond the outer row of terminals, so that the interruptions in themulti-branch leads can be formed readily.

Alternatively, or in combination with the above, the branches of amulti-branch trace may define gaps such that the gaps intervene betweenthe common section of the multi-branch trace and the select terminalsassociated with the various branches. Selective connections may beformed across such one or more of the gaps by conductive elements suchas wire bonds or solder masses so as to connect one or of the selectterminals to the common section. For example, the gaps can be bridgedusing solder applied in the package assembly plant with the sameequipment as is used to form vertical buses between the various units.Here again, the various units may be identical to one another until thetime the solder is applied, thus simplifying handling and stocking ofthe units.

A further aspect of the invention provides methods of making asemiconductor chip assembly. A method according to this aspect of theinvention includes the step of providing a plurality of units. Hereagain, each unit desirably includes at least one semiconductor chiphaving at least one chip select contact and a plurality of othercontacts and also includes a circuit panel having chip select terminals,other terminals and traces extending on or in the panel connected to theterminals. As discussed above, at least one trace of each paneldesirably is a multi-branch trace including a common section and pluralbranches connected to different ones of the chip select terminals, andthe contacts of the at least one chip in each unit desirably areconnected to the traces of the circuit panel in that unit so that thechip select contacts are connected to the common sections of themulti-branch traces. The method according to this aspect of theinvention desirably includes the step of selectively interrupting thebranches of the multi-branch traces so that the common section of amulti-branch trace in each unit is connected to less than all of thechip select terminals of that unit. The method preferably includes thestep of stacking the units and interconnecting terminals of differentunits to one another to form vertical buses.

The selectively interrupting step desirably is performed so that thechip select terminals of chips in different units are connected todifferent ones of the vertical buses. Most preferably, prior to the stepof selectively interrupting the multi-branch traces, the units aresubstantially identical to one another. The step of selectivelyinterrupting the multi-branch traces may be performed at any time duringor after formation of the units. In one arrangement, the step ofproviding the units includes connecting the chips to the traces using atool such as a thermosonic bonding tool, and the step of selectivelyinterrupting the branches is performed by engaging the same tool withthe branches as part of the same processing operation.

In another arrangement, the step of selectively interrupting thebranches is performed later as, for example, just prior to the stackingstep. Thus, the units may be provided as substantially identicalelements which may be handled and stocked as mutually interchangeableparts. Here again, the dielectric layers of the various units mayinclude interruption openings extending through the dielectric layers,and the branches of the multi-branch traces may extend across theseinterruption openings prior to the severing step. The step ofselectively interrupting the branches may include breaking the branchesat these interruption openings. Alternatively, the interruption openingsmay be formed at the same time as the branches are broken as, forexample, by removing small regions of each multi-branch trace andportions of the dielectric layers underlying these regions, such as bypunching the circuit panels to form the interruption openings while alsobreaking the branches of the traces.

Because the units are substantially identical to one another and can betreated as parts interchangeable with one another up to and includingthe step of severing the branches, handling and stocking of the units incommerce is substantially simplified. For example, the units can befabricated at a chip packing plant arranged to handle bare semiconductorchips and to mount the bare semiconductor chips to the circuit panels ofthe individual units. The stacking operation can be performed in acircuit board stuffing plant having tools and equipment adapted forsurface-mounting packaged chips to circuit boards. Indeed, the stackingoperation can be performed concomitantly with mounting the assembly to acircuit board. For example, the units can be stacked and the solderballs joining the various units can be reflowed at the same time as thesolder balls joining the bottom unit in the stack to the circuit boardare reflowed.

A further aspect of the invention provides an in-process collection ofinterchangeable semi-finished units usable in a stacking process andassembly as discussed above.

Another aspect of the invention provides another method of making asemiconductor chip assembly. A method according to this aspect of theinvention includes the step of providing a plurality of units. Hereagain, each unit desirably includes at least one semiconductor chiphaving at least one chip select contact and a plurality of othercontacts and also includes a circuit panel having chip select terminals,other terminals and traces extending on or in the panel connected to theterminals. As discussed above, at least one trace of each paneldesirably is a multi-branch trace including a common section and pluralbranches. Each of the plural branches is arranged on the circuit panelsuch that a gap is between each of the branches and a corresponding oneof the select terminals. The method according to this aspect of theinvention desirably includes the step of selectively connecting one, ormore, of the branches of the multi-branch traces so that the commonsection of a multi-branch trace in each unit is connected to less thanall of the chip select terminals of that unit. The method preferablyincludes the step of stacking the units and interconnecting terminals ofdifferent units to one another to form vertical buses.

The selectively connecting step desirably is performed so that the chipselect terminals of chips in different units are connected to differentones of the vertical buses. Most preferably, prior to the step ofselectively connecting the multi-branch traces, the units aresubstantially identical to one another. The step of selectivelyconnecting the multi-branch traces may be performed during formation ofthe units zzz.

A further aspect of the invention provides additional semiconductor chipassemblies. A chip assembly according to this aspect of the inventionalso includes a plurality of units, each including a semiconductor chiphaving contacts on a front surface, and including a circuit panel havinga central region and a peripheral region. The panel desirably includes adielectric layer having first and second surfaces and at least one bondwindow extending between the first and second surfaces in the centralregion. The panel also includes a plurality of terminals in theperipheral region, the terminals being exposed at both the first andsecond surfaces. Preferably, the dielectric layer has a plurality ofterminal apertures extending between the first and second surfaces inthe peripheral region and the terminals are pads aligned with theterminal apertures. The chip is disposed with the front surface of thechip facing toward a surface of the panel in the central region and thecontacts of the chip are connected to the traces on the panel in the atleast one bond window. The units are superposed on one another in astack so that the rear surface of a chip in one unit faces toward asurface of the dielectric layer in a next adjacent unit. The units mostpreferably bear on one another in at least those portions of the centralregions occupied by the traces. A plurality of conductive masses aredisposed between the terminals of the units and connect the terminals ofthe adjacent units to one another.

In one arrangement, the traces of each unit extend along the firstsurface of the dielectric layer in that unit, and the front surface ofthe chip in each unit faces toward the second surface of the dielectriclayer in that unit. In a chip assembly of this type, at least some ofthe units desirably include heat transfer layers overlying the traces ofsuch units, and these units bear on one another through the heattransfer layers. Thus, the heat transfer layer of each such unitdesirably abuts the rear surface of the chip in the next adjacent unit.The heat transfer layers of these units desirably extend across the bondwindows in the dielectric layers of these units and are substantiallyflat, at least in the region extending across the bond windows. Suchunits desirably further include an encapsulant at least partiallyfilling the bond windows. During manufacture, the heat transfer layersmay serve as masking layers which confine the encapsulant so that theencapsulant does not protrude beyond the dielectric layer. As furtherdiscussed below, the flat heat transfer layers allow close engagement ofthe units with one another and good thermal contact between adjoiningunits. These features contribute to the low height of the assembly andpromote effective heat dissipation from chips within the assembly.

In an assembly according to a further aspect of the invention, the heattransfer layer may be present or may be omitted, but the encapsulantdefines a surface substantially flush with the first surface of thedielectric layer or recessed relative to such surface. Where the heattransfer layer is omitted, the dielectric layer of each unit may beardirectly on the rear surface of the chip in the next adjoining unit.

A chip assembly according to another aspect of the invention alsoincludes a plurality of units. Each unit includes a circuit panel andmay include one or more chips. Each circuit panel has a number ofterminals and traces extending on or in the panel. The traces areelectrically connected between the contacts of the one or more chips andthe terminals. The units are superposed on one another in a stack. Aplurality of conductive masses are disposed between the terminals of theunits and connect the terminals of the adjacent units to one anotherforming vertical buses. The top-most unit includes one or moretermination elements, and desirably an array of plural terminationelements, such that one, or more, signals, received from one, or more,of the vertical buses are electrically terminated. The terminationelements desirably provide electrical characteristics at the upper endsof the vertical buses which mitigate signal reflection along the buses.

A chip assembly according to another aspect of the invention alsoincludes a plurality of units. Each unit includes a circuit panel andmay include one or more chips. Each circuit panel has a number ofterminals and traces extending on or in the panel. The traces areelectrically connected between the contacts of the one or more chips andthe terminals. The units are superposed on one another in a stack. Aplurality of conductive masses are disposed between some of theterminals of the units and connect those terminals of the adjacent unitsto one another forming vertical buses. Additionally, one, or more,passive elements as, for example, resistors, capacitors and inductorsare disposed between other terminals of the units such that thoseterminals of the adjacent units are electrically connected through thepassive element or elements.

A chip assembly according to yet another aspect of the invention alsoincludes a plurality of units. Each unit includes a circuit panel andmay include one or more chips. Each circuit panel has a number ofterminals and traces extending on or in the panel. The traces areelectrically connected between the contacts of the one or more chips andthe terminals. The units are superposed on one another in a stack. Aplurality of conductive masses are disposed between the terminals of theunits and connect the terminals of the adjacent units to one anotherforming vertical buses. A plurality of the vertical buses around atleast a portion of the periphery of the chip assembly are connected toground or to another source of constant potential. These bussescooperatively define a Faraday cage around at least a part of theperiphery of the stacked assembly. Preferably, the top-most unitincludes a conductive plane such as a ground plane. These vertical busesconstituting elements of the Faraday cage desirably are connected to theconductive plane so that the conductive plane forms a part of theFaraday cage. A stacked assembly in accordance with this aspect of theinvention provides economical electromagnetic shielding.

These and other objects, features and advantages of the presentinvention will be more readily apparent from the detailed description ofthe preferred embodiments set forth below, taken in conjunction with theaccompanying drawings.

BRIEF DESCRIPTION OF THE DRAWINGS

FIG. 1 is a top plan view of a circuit panel used in one embodiment ofthe invention.

FIG. 2 is a diagrammatic elevational view of a stacked package using thecircuit panel of FIG. 1.

FIG. 3 is a diagrammatic sectional view of a stacked package inaccordance with a further embodiment of the invention in conjunctionwith a circuit board.

FIG. 4 is a view similar to FIG. 1, but depicting a circuit panel inaccordance with a further embodiment of the invention.

FIG. 5 is a view similar to FIG. 2, but depicting a stacked packageusing the circuit panel of FIG. 4.

FIG. 6 is a diagrammatic plan view of a circuit panel used in yetanother embodiment of the invention.

FIG. 7 is a diagrammatic sectional view of a stacked package made usingthe circuit panel of FIG. 6.

FIG. 8 is a diagrammatic plan view of a translation panel used in afurther embodiment of the invention.

FIG. 9 is a diagrammatic sectional view of a package using thetranslation panel of FIG. 8.

FIG. 10 is a diagrammatic sectional view of a stacked package accordingto a further embodiment of the invention.

FIG. 11 is a fragmentary view of a portion of a package element inaccordance with another embodiment of the invention.

FIGS. 11A-11C are fragmentary sectional views depicting a portion of thepackage element of FIG. 11 during successive stages of a process inaccordance with a further embodiment of the invention.

FIG. 12 is a fragmentary, diagrammatic plan view of a package unit inaccordance with a further embodiment of the invention.

FIG. 13 is a fragmentary plan view on an enlarged scale of the unitshown in FIG. 12.

FIG. 14 is a fragmentary, sectional elevational view taken along line14-14 in FIG. 13.

FIG. 15 is a fragmentary, diagrammatic plan view of a circuit panel inaccordance with yet another embodiment of the invention.

FIG. 16 is a fragmentary, diagrammatic perspective view of an in-processassemblage including a plurality of units formed using the circuitpanels of FIG. 15.

FIG. 17 is a diagrammatic elevational view of a cutting tool usable withthe circuit panel and units of FIGS. 15 and 16.

FIG. 18 is a fragmentary, diagrammatic plan view of a circuit panel inaccordance with yet another embodiment of the invention.

FIG. 19 is a fragmentary, diagrammatic elevational view of an assemblyformed from the circuit panel of FIG. 18.

FIG. 20 is a fragmentary, diagrammatic sectional view of a unit inaccordance with yet another embodiment of the invention.

FIG. 21 is a fragmentary view of a portion of a package element inaccordance with another embodiment of the invention.

FIG. 22 is a fragmentary view of a portion of a package element inaccordance with another embodiment of the invention.

FIG. 23 is a fragmentary view of a portion of a package element inaccordance with another embodiment of the invention.

FIGS. 24 and 25 are diagrammatic sectional views of a stacked packagemade using the portion of the package element of FIG. 23.

FIG. 26 is a diagrammatic view depicting one embodiment of a terminationelement.

FIG. 27 is a diagrammatic sectional view of a stacked package accordingto a further embodiment of the invention having a termination element.

FIG. 28 is a fragmentary view of a portion of a package element used inpackage of FIG. 27.

FIG. 29 is a diagrammatic sectional view of a stacked package inaccordance with another embodiment of the invention.

FIG. 30 is a fragmentary diagrammatic sectional view of a stackedpackage in accordance with another embodiment of the invention.

FIG. 31 is an elevational view of a portion of an assembly in accordanceanother embodiment of the invention.

FIG. 32 is a top plan view of a unit used in another embodiment of theinvention.

FIG. 33 is a diagrammatic elevational view of a stacked packageincorporating the unit of FIG. 32.

FIG. 34 is a top plan view of a unit used in another embodiment of theinvention.

DETAILED DESCRIPTION

A package in accordance with one embodiment of the invention uses aplurality of package elements 20, each such element being in the form ofa circuit panel. Each such circuit panel may include a dielectric layerin the form of a thin, flexible dielectric tape as, for example, a layerof reinforced or unreinforced polyimide, BT resin or the like on theorder of 25-100 μm thick, most preferably 25-75 μm thick. Alternatively,each panel may include a dielectric such as a fiberglass-reinforcedepoxy as, for example, an FR-4 or FR-5 board. The panel has numerousterminals 22 disposed in rows within a peripheral region of the panel,adjacent the edges 24 of the panel. In the embodiment illustrated, rowsof terminals are provided along all four edges. However, the terminalscan be provided adjacent less than all of the edges as, for example, intwo rows adjacent to two opposite edges of the panel. Each terminal 22may be in the form of a flat, relatively thin disc of copper or othersuitable metallic material on a first surface 26 of the panel (thesurface visible in FIG. 1). As best seen in FIG. 2, the panel also hasholes 28 extending through it in alignment with terminals 22. Each suchhole extends between the first surface 26 of the panel and the opposite,second surface 30.

Each panel 20 further has an elongated bond window 32 extending adjacentthe center of the panel. The panel further has a large number of leads36. Each lead includes a trace 38 extending along the first surface 32of the panel and a connection section 40 formed integrally with thetrace projecting from the trace across the bond window. In theunassembled state depicted in FIG. 1, each connection section isconnected by a frangible element 42 to an anchor section 44 projectingfrom the side of the bond window opposite trace 38. The traces andanchor portions are arranged in a row extending along the length of thebond window. Different traces extend to opposite sides of the bondwindow, so that some of the connection sections 40 project into the bondwindow from one side, whereas others project into the bond window fromthe opposite side. The arrangement of the traces and their connectionsections may be substantially as shown in U.S. Pat. No. 5,489,749, thedisclosure of which is hereby incorporated by reference herein.

The terminals 22 include a first set of select terminals 22A-22D; asecond set of select terminals 22E-22H; as well as other terminals,referred to herein as non-select terminals, as, for example, terminals22J and 22K. Each trace 38 includes a common section 46 adjacent to andconnected to a connection section 40. Some of the traces are connectedto the non-select terminals. These traces have common sections 46 whichextend all the way to the associated terminals, such as to terminals 22Jand 22K, so that the common section 46 of each such trace is connecteddirectly with a non-select terminal.

Those traces 38 associated with the select terminals are multi-branchedtraces 50. Each such multi-branched trace has a plurality of branchesconnected to its common section 46 and connected to one of theassociated select terminals. For example, trace 38A includes branch 50Aconnected to select terminal 22A; branch 50B connected to selectterminal 22B; branch 50C connected to select terminal 22C; and branch50D connected to select terminal 22D. Trace 38A also includes adistribution section 52A extending transverse to the common section 46Aand interconnecting the various branches 50A-50D with the commonsection. Trace 38E associated with terminals 22E-22H is also amulti-branched trace and has a similar set of branches 50E-50H anddistribution section 52E, so that all of the branches 50E-50H areconnected to the common section 46E of the trace and to its connectionsection 40E. The dielectric of panel 20 has disconnection apertures 54aligned with the branches 50 of each multi-branched trace 38, so thateach such branch extends across a disconnection aperture. Thedisconnection apertures are disposed adjacent to the select terminals22A, 22B, etc.

The terminals and the leads, including the traces and connectionsections, are formed as a single layer of metallic features on the firstsurface of the panel. These metallic features desirably are less thanabout 30 μm thick, typically about 5-25 μm thick as, for example, about20 μm thick. A thin adhesive layer (not shown) optionally may beprovided between the dielectric layer 20 and the metal layer. Thisadhesive layer should also be as thin as practicable, desirably about 15μm or less thick. The terminals and traces can be formed by conventionalprocesses used in manufacture of tape automated bonding tapes and thelike as, for example, by etching a laminate including a layer of copperor other metal and the dielectric material which forms the panel so asto remove portions of the metallic layer. Alternatively, the terminalsand traces can be formed by a deposition process such as electrolessplating and/or electroplating. The bond window, the holes associatedwith the terminals and the disconnection apertures may be formed byetching or ablating the dielectric material.

The stacked chip assembly includes a plurality of units 56 (FIG. 2).Except as otherwise stated, each unit 56 is identical to each other unit56 in the stack. Each such unit includes a panel or chip carrier 20 asdiscussed above with reference to FIG. 1 and a chip 58 associated withthat panel. Each such chip has a front or contact bearing surface 60 anda rear surface 62. The front surface 60 of each chip has contacts 64arranged in rows adjacent the center of the chip. The chip also hasedges 66 bounding the front and rear surfaces 62. The thickness t of thechip (the dimension between the front surface 60 and back surface 62)typically is substantially smaller than the other dimensions of thechip. For example, a typical chip may be about 100-500 microns thick andmay have horizontal dimensions (in the plane of the front and rearsurfaces) of about 0.5 cm or more. The front surface 60 of the chipfaces towards the second surface 30 of the associated panel 20.

A layer of adhesive 68 is disposed between the chip and the panel ofeach unit. The adhesive layer 68 defines an aperture in alignment withthe bond window. Adhesive layer 68 may be provided by applying a liquidor gel material between the chip and the panel at the time of assemblyor by providing a porous layer such as an array of small resilientelements between the layers and injecting a flowable material into suchlayer as taught, for example, in certain embodiments of U.S. Pat. Nos.5,659,952 and 5,834,339, the disclosures of which are herebyincorporated by reference herein. Preferably, however, the adhesivelayer is provided as one or more solid or semi-solid pads havingsubstantially the same horizontal extent as the desired adhesive layerin the final product. These pads are placed between the chip and panelduring assembly. For example, the pad may be pre-assembled to the panelor to the chip before the chip is juxtaposed with the panel. Such asolid or semi-solid pad can be placed quite accurately in relation tothe chip and the panel. This helps to assure that the pad does not coverterminals 22, even where there is only a small clearance between thenominal position of the pad edge and the terminals. Such a pad mayinclude an uncured or partially cured layer and other adhesion-promotingfeatures as discussed, for example, in U.S. Pat. No. 6,030,856, thedisclosure of which is hereby incorporated by reference herein.Alternatively or additionally, the pad may be provided with a thin layerof a flowable adhesive on one or both surfaces, and this layer may be anon-uniform layer as described in U.S. Pat. No. 5,548,091, thedisclosure of which is hereby incorporated by reference herein, to helpprevent gas entrapment in the layer during assembly. Adhesive layer 68desirably is as thin as practicable as, for example, about 10-125 μmthick, most preferably about 25-75 μm.

The chip 58 of each unit is aligned with the central region of theassociated panel, so that the rows of contacts 64 are aligned with thebond window 32 in the panel. The connection section 40 of each lead isconnected to a contact 64 of the chip. During this process, theconnection section of each lead is detached from the anchor section 44of the lead by breaking the frangible section 42 of the lead. Thisprocess may be performed as described in the aforementioned U.S. Pat.No. 5,489,749 by advancing a tool (not shown) such as a thermal,thermosonic or ultrasonic bonding tool into the bond window of the panelin alignment with each connection section so that the tool captures theconnection section and forces it into engagement with the appropriatecontact. The common section 46 of the trace 38 in each lead (FIG. 1) isconnected by a connection section 40 to a contact on the chip. Thearrangement of the contacts and connection sections is selected so thatthe common sections 46A and 46E of multi-branched traces 38A and 38E areconnected to select contacts on the chip, i.e., to contacts of the chipwhich are not to be connected in parallel with corresponding contacts onall of the other chips in the stack. The common sections of the othertraces are connected to the non-select contacts, i.e., contacts of thechip which are to be connected in parallel with corresponding contactsof the other chips in the stack.

Each unit 56 further includes a solder mask layer 70 (FIG. 2) overlyingthe traces and terminals in the peripheral region of the panel. Thesolder mask layer has apertures aligned with the terminals 22. Thesolder mask layer can be applied as a conformal coating or sheet byconventional processes. Each unit further includes a heat transfer layer76 overlying the traces 38 and the first surface 26 of the panel in thecentral region of the panel aligned with the chip 58. As furtherdiscussed below, the heat transfer layer will establish intimate contactwith the rear surface of the chip in the next adjacent unit of thestack. The heat transfer layer may be formed from a material such as agel or grease loaded with a thermally conductive filler, or from amaterial which can be brought to a deformable condition during assemblyas, for example, a thermoplastic material or an uncured or partiallycured epoxy or other reactive resin. Desirably, the heat transfer layeris a dielectric material and hence does not electrically short thevarious traces to one another. The heat transfer layer may be formedintegrally with the solder mask layer so that a central portion of thesolder mask layer, aligned with chip 58, forms the heat transfer layer.

The heat transfer layer, whether formed integrally with the solder masklayer or separately from the solder mask layer, desirably is as thin aspracticable as, for example, about 40 μm thick or less, and desirablyabout 30 μm thick or less. An integral solder mask layer and heattransfer layer may be provided as a conformal coating having a thicknessof about 5-20 μm in those regions of the coating overlying the tracesand about 10-40 μm thick in those regions disposed between the traces.Such a coating adds only about 5-20 μm to the overall thickness of theunit. As seen in FIG. 2, the central portion of the heat transfer layeror solder mask layer bridges across the aperture 32 in the dielectriclayer. Preferably, the central portion of the heat transfer layer orsolder mask layer is substantially planar, and does not bulgesubstantially away from dielectric layer 20.

An encapsulant 33 may be provided in aperture 32, surrounding theconnection sections 40 of the leads. The encapsulant may be separatefrom the adhesive layer 68 and may be introduced using the techniquesdisclosed in U.S. Pat. Nos. 6,232,152 and 5,834,339, the disclosures ofwhich are incorporated by reference herein. As disclosed in certainpreferred embodiments taught in the '152 and '339 patents, the layerattaching the chip to the dielectric layer (adhesive layer 68) maydefine a channel extending to one or both edges of the chip, and theencapsulant may be introduced into this channel at the edges of thechip. Alternatively, where the adhesive layer is formed in whole or inpart by a flowable material introduced between the chip and thedielectric layer as discussed above, the encapsulant may be formed bythe flowable material. In either process, the heat transfer layer 76 (orinternal heat transfer and solder mask layer) covers the bond window inthe dielectric layer so that the encapsulant cannot project beyond thefirst surface 76 of the dielectric layer.

During assembly of each unit, some of the branches of eachmulti-branched trace are broken so as to disconnect the terminalsassociated with those particular branches from the common section of themulti-branched trace. Preferably, all but one branch of eachmulti-branched trace is broken, leaving only one select terminalconnected to the common section of each multi-branched trace. Thebranches may be broken by advancing a tool into the disconnectionapertures 54 associated with the branches to be broken. The tool may bethe same tool used to perform the bonding operation on the connectionsections of the leads. To facilitate the breaking operation, thebranches may be provided with frangible sections weaker than theremainder of the branch, such as narrowed sections (not shown), inalignment with the disconnection apertures. During the breaking process,the terminals 22 adjacent to the branches to be broken serve as anchorsfor the branches so that the branches tend to break rather than becomingdetached from the dielectric of panel 20. The broken ends of thebranches are not connected to any portion of the chip. The adhesivelayer 68 preferably does not include apertures aligned with thedisconnection apertures and the broken ends of the branches becomeburied in the adhesive. Alternatively, the broken ends of the branchesmay contact the dielectric passivation layer (not shown) on the surfaceof the chip.

Different units have different ones of the branches connected toterminals after the breaking step. For example, in the four-unitassembly depicted in FIG. 2, the top unit 56A may have the commonsection 46A of multi-branched trace 38A connected only to terminal 22Aof set 22A-22D and has the common section 46E of trace 38E connectedonly to terminal 22E of set 22E-22H. In the next unit 56B, commonsection 46A is connected only to terminal 22B whereas common section 46Eis connected to terminal 22F. The next unit 56C has sections 46A and 46Econnected to terminals 22C and 22G respectively, whereas the bottom unit56D has the same common sections connected to terminals 22D and 22H.

The units are stacked one on top of the other as illustrated in FIG. 2.Each terminal 22 is connected to the corresponding terminal of the nextadjacent unit via a solder ball 78. The solder balls 78 serve asconductive elements which join the corresponding terminals of thevarious units into vertical conductive buses. For example, terminal 22J(FIG. 1) of each unit is connected on the same vertical bus with thecorresponding terminals 22J of the other unit. Each solder ball makescontact with the terminal of one unit through an aperture in the soldermask layer 74 and with a terminal of the other unit through an aperture28 in the dielectric layer of the panel 20 in that unit. The heattransfer layer 76 (or the combined heat transfer and solder mask layer,where such a combined layer is employed) on each unit other than bottomunit 56D makes intimate contact with the rear surface 62 of the chip inthe next lower unit in the stack. During assembly, the solder balls arepartially or entirely melted or “reflowed.” The solder mask layer 74 andthe dielectric layers of the panels prevent spreading of the solderalong the lengths of the traces 38 during the reflow operation. The heattransfer 76 layers may be momentarily softened during the assemblyprocess to assure intimate contact. Alternatively, where the heattransfer layers are formed from an initially soft or flowable materialsuch as a curable epoxy, the heat transfer layers may be cured duringassembly after being brought into intimate contact with the chip of thenext lower assembly.

Prior to assembly of the stack, the individual units can be tested in atest socket having contacts corresponding to the locations of theterminals. Typically, the solder balls are bonded to the terminals ofeach unit so that they project from the first surface 26 of the paneland the unit is tested with the solder balls in place. For example, thetest socket may have openings adapted to engage the solder balls.Because all of the units have terminals and solder balls in the samepattern, the single test socket can be used to test all of the units.

The resulting package may be assembled to a circuit board usingconventional surface mounting techniques. The solder balls 78 of thelower most unit 56D can be reflowed and bonded to contact pads 80 of acircuit board 82, partially depicted in FIG. 2. Thus, each vertical busis placed in electrical contact with an individual contact pad 80 of thecircuit board. The heat transfer layer 76 of the bottom unit 56D may bein contact with a feature of circuit board 82 as, for example, a largethermal pad 84. A metallic plate 86 may be provided as part of thepackage or mounted to the circuit board prior to assembly of thepackage. This plate serves as a heat conductor between the thermal layer76 and the circuit board. Where the plate 86 is provided as a part ofthe package, the plate or the pad may carry a layer of solder (notshown) so that the plate is reflow-bonded to the pad 84 when the solderballs are bonded to the contact pads. Alternatively, the heat transferlayer 76 of the lower-most unit may be thick enough so that it makesdirect contact with a feature of the circuit board itself. In a furthervariant, the heat transfer layer of the lower-most unit may be omitted.

The completed package provides numerous advantages. As discussed above,the select contacts of chips in different units are connected todifferent select terminals and therefore connected to different verticalbuses. By routing selection signals to the contact pads of the circuitboard associated with these buses, it is possible to apply a selectionsignal to a select contact in a chip of only one unit. The verticalbuses formed by the interconnected solder pads are quite short andprovide low electrical impedance. Also, the traces provide a relativelylower impedance path. Typical traces have an inductance of about 5nanohenries or less. Moreover, signal propagation delays between thecontact pads of the circuit board and the contacts of any given chip arenearly the same as the signal propagation delays between the contactpads of the circuit board and the contacts of any other chip in thepackage. The units can be made economically, using “single-metal”circuit panels having conductive features on only one side. The entirepackage has a height which is determined in part by the thicknesses ofthe individual chips. Merely by way of example, one package whichincorporates four units, each having a chip about 125 microns thick, hasan overall height of about 1.5 mm.

The low overall height of a package is due in part to the smallthickness of the elements other than the chips which determine thespacing between adjacent chips in the stack. As discussed above, withinthe central region of each unit aligned with the chip of such unit, theunit desirably includes only the adhesive layer 68, the leads or traces38 and the heat transfer or solder mask layer and, optionally, a furtheradhesive layer between the dielectric layer and the metallizationforming the leads. The distance d between corresponding features ofadjacent units as, for example, the distance d between the secondsurface 30 of the dielectric layer 20 in unit 56A and the correspondingsurface of the dielectric layer in unit 56B will be equal to thethickness t of chip 58B disposed between these layers plus the aggregatethickness of the aforementioned layers constituting the central portionof each unit. Most preferably, the distance d between adjacent units isequal to the thickness t of the chip plus about 250 μm or less, mostpreferably about 200 μm or less. Still smaller distance d can beachieved when the various layers are selected to provide the minimumheight.

Because the heat transfer layer or combined solder mask layer and heattransfer layer is substantially flat, it can make good, intimate contactwith the rear surface of the chip. This helps to provide both a lowoverall height and good heat transfer between units. Heat evolved in thechips of units in the middle of the stack can be dissipated by heattransfer to adjacent units through the top or bottom of the stack andfrom the top or bottom of the stack to the environment as, for example,to the circuit board 82 or to the surrounding atmosphere. To assure goodheat transfer, and to provide the minimum overall height, it isdesirable to assure that the central region of each unit is brought intoabutting contact with the chip in the next adjacent unit during thestacking and reflow operations. It is also desirable to assure that theunits align with one another in the horizontal direction during thestacking and reflow process, using the self-centering action provided bythe surface tension effects of the solder balls. If the height of thesolder balls is selected to provide a nominal clearance of about 10-15μm prior to reflowing, then upon reflowing the solder balls willinitially align the units with one another and, additionally, the solderwill collapse to bring the units into abutment with one another.Alternatively or additionally, the units may be pressed together duringreflow to assure abutment, and may be aligned with one another usingappropriate fixturing or robotic systems as, for example, systemsequipped with robotic vision components.

In a variant of the assembly method discussed above, the units can befabricated without breaking the branches 50 of the multi-branchedtraces. These units can be handled and stocked as interchangeable partsprior to assembly with one another and with the circuit board. Thebranches are broken in a separate operation, desirably immediately priorto assembly. Thus, the step of selectively interrupting the branchesdesirably is performed in the same production plant or facility as thestep of stacking the units. The separate branch-breaking operation doesnot require the same degree of precision required for bonding theconnection sections of the leads and hence can be performed byless-precise equipment. Moreover, the ability to handle and stock onlyone type of unit throughout the entire supply chain up to assemblysimplifies handling and distribution. Thus, units having identicalchips, traces and terminals, prior to breaking the branches, areinterchangeable with one another and can be provided in bulk, as acollection of interchangeable semi-finished articles. As used in thiscontext, the term “identical” refers to the nominal configuration of thechips, traces and terminals, without regard for unit-to-unit variationswhich necessarily occur in any manufactured article.

The stacking and branch-breaking operations desirably are performed in aproduction plant adapted for attaching packaged semiconductor chips,modules and other components to the circuit board, an operation commonlyreferred to in the industry as “board stuffing.” Board stuffing plantswhich employ surface mounting technology are commonly equipped withfacilities for handling and placing components onto the circuit board,and with reflow equipment for momentarily heating the circuit board withthe components thereon to fuse solder or otherwise activate bondingmaterials between the components and the contacts of the circuit board.The stacking operation can be performed using substantially the sametechniques and procedures used for mounting elements to circuit panels.Only the minimal additional operation of breaking the branches isrequired.

In yet another variant, the stacking operation can be performedconcomitantly with assembly of the stack to the board. That is, theindividual units can be stacked on the circuit board, one above theother and temporarily held in place on the board as, for example, by atemporary clamping fixture, gravity, by adhesion between units, by fluxat the terminals, or by some combination of these. In this assembledcondition, the solder balls or conductive elements 78 associated withthe bottom unit 56 d overly the contact pads of the circuit board andthe solder balls of the other units overlies the terminals of the nextlower unit in the stack. After stacking, the entire stack and circuitpanel are subjected to a reflow operation sufficient to fuse the bottomsolder balls to the contact pads of the circuit board and to fuse thesolder balls of the other units to the terminals of the adjacent units.This reflow operation may be performed in conjunction with the reflowoperation used to attach other components to the board.

A package according to a further embodiment of the invention depicted inFIG. 3 is similar to the embodiment of FIGS. 1 and 2 discussed aboveexcept that the units 156 are inverted so that the chip 158 incorporatedin each unit is disposed towards the bottom of the unit whereas thecircuit panel or package element 120 of each unit is disposed above thechip of that unit. Also, the solder balls 178 associated with each unitare disposed on the second or chip-facing side 130 of the panel ratherthan on the first or chip-remote side 126 of the panel. Stated anotherway, in this arrangement the solder balls are disposed on the same sideof the panel as the chip. This arrangement provides lower overall heightin the completed assembly.

A thermal spreader 190 is mounted to the top unit 156A, in contact withthe heat transfer layer 176A of the top unit. The thermal spreader 190may be formed from a metal or other thermally conductive material andmay incorporate features such as ribs or fins (not shown) fordissipating heat into the surroundings. Also, the thermal spreader mayhave walls extending downwardly adjacent the edges of the package towardthe circuit board 182 to promote the heat transfer between the spreaderand the circuit board. The heat transfer layer 176 provided on the firstor chip-remote surface 126 of the top most unit 156A conforms closely tothe surface of the panel 120 in such unit and to the traces 156. Asdiscussed above, this layer may be a dielectric layer to maintainelectrical insulation between the traces of the top unit and thespreader. Alternatively or additionally, the solder mask layer 174 ofthe top-most unit may extend over the traces, into the central region ofthe panel to provide electrical insulation for the traces. Similarthermal conductive layers 176 are provided over the central regions ofthe panels in the other units. Here again, the solder mask layer orother dielectric layer can be used to insulate the traces if the heattransfer layer is electrically conductive. As discussed above inconnection with FIGS. 1 and 2, these thermally conductive layers promoteintimate contact and heat transfer between the various units in thestack. This, in turn enhances heat dissipation from the inner units ofthe stack.

Where solder balls 178 are provided on the same side of the tape as thechip, the solder balls may be surrounded wholly or partially by astiffening layer (not shown) as disclosed in a co-pending, commonlyassigned U.S. Patent Application Ser. No. 60/314,042, filed Aug. 22,2001, and in the PCT international application claiming priority ofsame, Serial No. PCT/US02/26805, the disclosures of which are herebyincorporated by reference herein. As disclosed in the '042 application,a stiffening layer can be formed by a flowable material as, for example,an epoxy or encapsulant such as an epoxy or encapsulant injected betweenthe chip and the panel of a unit to form the adhesive layer 168. Thestiffening layer extends towards the periphery of the panel anddesirably surrounds the solder balls where the stiffening layerreinforces the panels for ease of handling during assembly. Because thislayer is disposed outside of the central region, beyond the areaoccupied by the chips, it does not add to the height of the stack.

The rear surface 162 of the chip in the bottom unit 156D faces towardthe circuit board 182. Rear surface 162 may be physically attached tothe circuit board and placed in more intimate thermal communication withthe circuit board by a thermal layer 192 provided between the rearsurface of the chip and the board. Such a thermal layer may be formedfrom a thermally conductive material such as a gel or grease with aconductive filler or from a solder which is reflowed when the solderballs of the bottom unit are reflowed to attach the terminals to thecontact pads 180 of the circuit board.

The embodiment of FIGS. 4 and 5 is similar to the embodiment discussedabove with reference to FIGS. 1 and 2 except that the panel or chipcarrier 320 of the lower-most unit is provided with additional “dummy”terminals 323. Here again, all of the terminals and traces are providedas elements of a single metallic layer. Dummy terminals 323 are disposedin an array extending over the central region of the panel 320D in thebottom unit 356D. This panel also has peripheral terminals 322corresponding to the select terminals and non-select terminals discussedabove with reference to FIG. 1. Solder balls 379 are provided on thedummy terminals in the same manner as solder balls 378 are provided onthe other terminals. These solder balls serve as heat conductors betweenthe bottom unit and the circuit board when the package is mounted on acircuit board. As best seen in FIG. 4, the dummy terminals 323 may bedisconnected from the traces as shown for example at 323B. In thisarrangement, the traces 338 are routed around the dummy terminals.Alternatively or additionally as shown at 323C, dummy terminals can beconnected to the traces. This allows routing of the traces through thearea occupied by the dummy terminals and hence simplifies layout of thetraces on the panel.

In the embodiment depicted in FIGS. 6 and 7, the panels 420 of all ofthe units 456 except the bottom unit 456D are identical to the panelsdiscussed above with reference to FIGS. 1 and 2. Panel 420D of thebottom unit is a so called “two metal” panel having a layer of metallicfeatures 430 on the second or chip-facing side of the panel as well asseparate layer of metallic features on the first or chip-remote side.The layer of metallic features on the chip-facing side 430 includesperipheral terminals 425 and traces 439 corresponding to the terminals422 and traces 438 of the other panels in the stack. These terminals andtraces include terminals and traces essentially identical to theterminals and traces discussed above. The layer of metallic features onthe first or chip-remote side 426 of the panel includes an array ofboard connection terminals 423 disposed in a rectilinear grid extendingon the central region of the panel. This metallic layer also includesadditional traces 433 extending from the board connection terminals 423to vias 425. The vias 425 include holes extending through the panel andmetallic structures such as via liners extending through these holes.Additional traces 433 are connected to traces 439 by the metallicfeatures within the vias. When the package is mounted to the circuitboard, the board connection terminals 423 are connected to the contactpads of the circuit board, thus connecting the traces 439 and peripheralterminals 425 to the circuit board. This in turn connects the verticalbuses formed from the peripheral terminals 425 and the correspondingterminals 422 of the other panels with the contact pads of the circuitboard. In a variant of this approach, each branch 450 of themulti-branched traces may be provided with a separate via 425 and linkedto a separate interconnect trace 433 and board connection terminal 423.

The embodiment of FIGS. 8 and 9 uses panels 520 identical to the panelsdiscussed above with reference FIGS. 1 and 2 in all of the units 556.However, the terminals 522D, 556D are not connected directly to thecircuit panel thus, the terminals of this unit are not provided withsolder balls projecting downwardly. A further circuit panel ortranslator 501 overlies the chip-remote or first surface of panel 520D.The translator has board connection terminals 523 disposed in a gridlike pattern similar to the pattern of board connection terminals 423discussed above with reference to FIGS. 6 and 7. The translator also hasperipheral terminals 527 in a pattern corresponding to the pattern ofterminals 522 on the panels of the various units and connection traces533 interconnecting the connection terminals 523 with the peripheralterminals 527. The translator is juxtaposed with the panel of the lowermost unit so that the peripheral terminals of the translator are alignedwith the peripheral terminals 522D. Thus, each vertical bus defined byeach set of aligned peripheral terminals on the various panels 520 iselectrically connected with one peripheral terminal 527 of thetranslator and hence with one contact pad on the circuit board. Thisarrangement allows fabrication of a structure with a standard or gridlike terminal pattern for mounting on the circuit board with only asingle metal element. The terminals 522D of the bottom unit may besolder bonded to the peripheral terminals 527 of the translator when thesolder balls 578 of the next lower unit are reflowed. In a variant, thetranslator may include separate connections to separate board connectionterminals 523 associated with those peripheral terminals 527A-527D whichwill ultimately be connected to the buses associated with selectterminals on the various units. This assures that each bus connected toselect terminals will be connected to a unique contact pad on thecircuit board.

In a further variant, the translator itself may include one or moresemiconductor chips. For example, the translator may be a “bottom unit”of the type discussed in certain preferred embodiments of theco-pending, commonly assigned U.S. Provisional Patent Application Ser.No. 60/408,644, entitled “Components, Methods and Assemblies For StackedPackages,” filed on or about Sep. 6, 2002 and naming Kyong-Mo Bang asinventor, the disclosure of which is hereby incorporated by referenceherein. As further discussed in the '644 application, such a bottom unitincludes a bottom unit semiconductor chip and also includes topconnections adapted to receive additional microelectronic devices. Sucha bottom unit also may be mounted to a circuit board in a circuit boardstuffing plant and additional microelectronic devices, such as a stackedassembly as discussed herein may be mounted to the top connections ofthe bottom unit. Merely by way of example, the bottom unit chip may be amicroprocessor or other chip, whereas the chips in the stacked assemblymounted to the bottom unit may be memory chips which, in service,cooperate with the bottom unit chip.

The package illustrated in FIG. 10 is similar to the package shown inFIG. 3 except that the traces 638 of the panels 620 do not haveintegrally formed connection sections for bonding to the contacts 664 onthe chip 658. Instead, the traces terminate in bonding pads 637 adjacentthe bond window 632. Wire bonds 639 are provided between these bondingpads and the contacts 664 of the chip. Also, the package of FIG. 10includes only two units rather than four units. Larger numbers and oddnumbers of units also can be used in any of the foregoing structures.Wire bonded units also can be employed in the reverse orientation, i.e.,with the chip of each unit disposed above the panel of the unit asdiscussed with reference to FIGS. 1 and 2. Also, an encapsulant 601covers the wire bonds. The end caps may be integral with the thermallyconductive layer 678 overlying the remainder of the unit.

In a further variant (FIG. 11), a multi-branched trace 639 has a commonsection 646 which is adapted for connection to the chip contact 664. Thecommon section thus may have a bonding pad 637 for use with a wire bondconnection to the contact or else may have a connection section whichcan be directly bonded to the contact. The branches 650 of the trace,when initially fabricated, do not extend in an unbroken, continuous pathfrom the common section 646 to the various select terminals 622. Rather,each branch is initially fabricated with a gap 651. These gaps can beselectively closed as, for example, by applying a short conventionalwire bond 653 across the gap 651 of one branch. This embodiment is lesspreferred, as the additional wire bond introduces additional complexityand impedance and may lie above the plane of the surrounding panel.Desirably, the gaps in the branches are positioned in the peripheralregion of the circuit panel, outside of the region occupied by the chip658 (indicated in broken lines in FIG. 11), so that the wire bond 653extending across the gap will lie outside of the area occupied by thechip. Thus, a protruding wire bond in one unit and an encapsulant whichmay optionally be applied over such a protruding wire bond may projectvertically beside the chip in that unit or alongside the chip in thenext adjacent unit and, thus, will not add to the overall height of thestacked assembly.

In a variant of this approach, the conventional wire bond is replaced bya stud bump. As shown in FIG. 11A, the gap 651 in a branch 650 of amulti-branched trace is defined by a pair of pads 680 and 682. The pads680 and 682 are formed by portions of the branches exposed at a surface681 of the dielectric layer 684 of the circuit panel, such surface beingreferred to herein as the front surface. The pads desirably are formedfrom or plated with a material compatable with wire bonding as, forexample, gold. The pads desirably are flush with the surroundingdielectric or, more preferably, project slightly above the surroundingdielectric. In a bump-forming process, a wire bonding tool is positionedover the gap as shown in FIG. 11A. The wire bonding tool has a bore 686extending to a working surface 687, and may have a recess or chamfer 688at the juncture of the bore and the working surface. The wire bondingtool is connected to an ultrasonic vibration generator as, for example,by a “horn” which serves to transmit the ultrasonic vibrations to thetool. The horn and tool are mounted on a ram (not shown) which isarranged to move the tool upwardly and downwardly as seen in FIGS. 11Aand 11B. A fine wire 689, typically formed from gold or a gold alloy oraluminum or an aluminum alloy and most typically having a diameter ofabout 25 μm or less extends from a wire supply device (not shown)through bore 686 to the working surface 687. At the inception of thegap-closing process, the wire has a mass of the wire material in theform of a ball 690 at its end. The ball typically is about 40-80 μm indiameter. Such a ball can be formed by melting the end of the wire as,for example, by locally heating the end of the wire using a flame, hotgas jet electrical energy or radiant energy. The rear surface of thedielectric element, opposite from top surface 681, desirably issupported on a rest 692, which may be equipped with a heater (notshown). The wire, wire-bonding tool, rest, and associated equipment maybe substantially conventional elements of the type commonly employed inwire bonding operations.

The bonding tool 685 is forcibly advanced downwardly until the ball 690engages pads 680 and 680. To facilitate such engagement, the width W_(g)of gap 651 or distance between trace portions desirably is less than thediameter of ball 690 as, for example, about 40 μm or less, mostpreferably about 30-35 μm. Ultrasonic energy is applied though tool 685,and the ball is squeezed between the tool and the pads. Under theinfluence of the applied energy and force, the ball 690 deforms to forma “bump” 693 depicted schematically in FIG. 11B. Heat may be appliedthough rest 692 to facilitate the bonding operation. The conditionsused, such as the force applied by the tool, the frequency and intensityof ultrasonic energy, and the heating applied through the rest, may besimilar to those used in conventional ball wire bonding. The material ofthe ball bonds to the material of pads 680 and 682. In the next phase ofthe operation, the bonding tool is retracted upwardly away from the bump693 and the pads 680 and 682, while the wire supply apparatus is lockedso that the wire 686 cannot move relative to the bonding tool 685. Thisaction breaks the wire just above bump 693, thereby leaving the bump inplace at gap 651. The broken end of the wire is then heated to form anew ball so that the process can be repeated. Alternatively, the wirebonding tool 685 can be retracted upwardly away from the bump 693 whileallowing the wire to pay out from the tool. This leaves a portion of thewire extending between the bump 693 and the tool. Energy is applied tomelt the wire, thereby forming a new ball and freeing the wire from thebump. In either case, the bump forms a conductive bridge across the gap,and electrically interconnects the trace portions, as seen in FIG. 11C.By contrast, in a conventional wire bond, a length of wire is connectedby two separate bonds to the elements to be joined. Typically, the wirebetween the bonds is in the form of a loop. The bump formed inaccordance with FIGS. 11A-11C provides a compact, economical connectionbetween the trace portions. Preferably, the bump is covered by anencapsulant or otherwise physically protected. Bumps of this type can beused to make connections other than the connections within a branch of amulti-branched trace. For example, such bumps can be used to makeconnections between traces or other conductive elements on any circuitpanel having conductive elements separated from one another by a smallgap.

A unit in accordance with a further embodiment of the invention (FIG.12) incorporates a circuit panel or dielectric element 720 generallysimilar to the elements discussed above and having numerous terminals722 disposed thereon and connected to numerous leads 738. The terminalsinclude a first outer row 723 incorporating terminals 722A-722Fextending adjacent to a first edge 724 of the circuit panel. This row ofterminals defines an inner border. Terminals 722 may include additionalterminals as, for example, terminals 722G and 722H disposed further fromthe edge 724, as well as other terminals (not shown) on other parts ofthe circuit panel. The first outer row 723 defines an inner border 725at the edge of the terminals furthest from the first edge 724 of thecircuit panel, a center line 726 and an outer border 731 at the edgeclosest to edge 724.

Terminals 722C and 722D form a set of chip select terminals associatedwith a multi-branched lead 738C having a common section 746C adapted forconnection to a chip select contact 764 and also having branches 750Cand 750D connected to the common section. Branch 750C connects thecommon section to a chip select terminal 722C, whereas branch 750Dconnects the common section 746C to another chip select terminals 722D.As best seen in FIG. 13, branches 750C and 750D extend close to thefirst edge 724 of the circuit panel 720. Desirably, the branches extendto within about 1 mm and preferably within about 0.5 mm or less of thefirst edge 724, and most desirably within about 200 microns or less ofthe first edge. Branches 750C and 750D are disposed outwardly of theinner border 725 of the first outer row of terminal 723 and are alsodisposed outwardly of the center line 727 of this row, near the outerborder 731 of the row. The circuit panel 720 has disconnection openings754C and 754D in the form of notches extending inwardly from first edge724.

As best seen in FIG. 14, circuit panel 720 includes a structuraldielectric layer 726 defining the bottom or inner surface of the circuitpanel, a single layer of metallic features including the leads andterminals and, hence, including branch 750C, and a solder mask layer774. The base dielectric layer 726 and solder mask layer 774 areinterrupted in the disconnection openings or notches 754 such that thebranch 750C bridges across the disconnection opening. Notches 754C and754D extend inwardly from edge 724 to and slightly beyond branches 750Cand 750D. Because the branches are disposed close to the edge, thenotches need not extend far into the circuit panel from the edge.Desirably, the notches extend less than about 1.5 mm and more desirablyless than about 1.0 mm into the panel. The same structure is provided atbranch 750D and disconnection opening or notch 754D.

Thus, the branches 750 can be selectively broken by inserting a toolinto the notch as, for example, a punch 702 (FIGS. 12 and 13) into thenotches. The punch may be moved in a direction perpendicular to theplane of the circuit panel or parallel to the plane. A matching diehaving an opening shaped to closely conform to the punch may be providedbeneath the circuit panel, and the punch may move downwardly through thenotch into engagement with the die, breaking the branch lead in theprocess. Thus, branches 750C or 750D can be interrupted selectively sothat the common section 746C of lead 738C can be connected selectivelyto either, both or neither of terminals 722C and 722D. An additionalmulti-branch lead 738E (FIG. 12) is associated with a similar pair ofchip select terminals 722E and 722F and has a similar structure ofbranches and similar notches associated with the branches. As also seenin FIG. 12, some of the leads as, for example, lead 738A, are associatedwith two or more terminals 722A and 722H and permanently connected tothese terminals. Also, lead 738A is a wide, planar structure covering asignificant area on circuit panel 720. Further, some of the terminalsare unconnected to leads. Such unconnected terminals may be provided,for example, to provide a symmetrical pattern of terminals and, hence, asymmetrical structure of vertical conductors in the finished assembly.Also, in addition to the various units, the assembly may includeadditional electrical elements disposed at the top of the stack or,indeed, at any location within the stack. The additional verticalconductors formed by unconnected terminals can serve as additionalconductors extending to these elements.

The unit partially depicted in FIG. 15 has a circuit panel 820 having afirst edge 824 and having a first row of outer terminals 823 extendingalongside of edge 824, parallel to such edge, as well as an additionalrow 821 of terminals disposed inboard of the first outer row. Amulti-branched lead 838 has a common section 846 and branches 850A,850B, 850C and 850D extending to select terminals 822A, 822B, 822C and822D, respectively. Branches 850 are connected to the common section 846by intermediate sections 851. One such intermediate section connectsbranches 850A and 850B with the common section 846, whereas the otherintermediate section connects branches 850C and 850D with the commonsection. Here again, the branches 850 extend in whole or in partoutwardly beyond the center line 827 of the first outer row 823 ofterminals. However, as initially manufactured and as connected in asemi-finished unit with a chip, the circuit panel does not havedisconnection openings. Instead, branches 850 are selectively severed byforming notches 854 (seen in broken lines in FIG. 15) and breaking thebranches during such notch formation. For example, the circuit panel maybe selectively cut by a punch to form notches 854 where the branches areto be severed, but not form notches in other locations. For example, ifnotches 854 are formed in the pattern indicated in FIG. 15, branch 850Bwill remain unsevered and, hence, select terminal 822B will remainconnected to the common portion 846 of lead 838, but the remainingselect terminals will be disconnected. This operation desirably isperformed, as discussed above, prior to stacking and most desirably inthe same plant where the stacking is performed as, for example, in acircuit board stuffing plant.

As seen in FIG. 16, a large number of units may be provided as parts ofa large sheet. Thus, one or more of the dielectric layers forming thecircuit panels of the individual units form parts of continuous orsemi-continuous dielectric layers extending throughout the sheet or tape802. The sheet or tape may be provided with conventional registrationfeatures such as sprocket holes 804. Although the borders of the circuitpanels forming the individual unit 820 are delineated in FIG. 16 forclarity of illustration, it should be appreciated that at this stagethere may be no physical demarcation between adjacent units. The unitsare assembled in the manner discussed above by assembling semiconductorchips to the circuit panels of the individual units while leaving theunits connected in the sheet 802. At this stage, all of the units aresubstantially identical with one another. The assembly of theseidentical units can be handled and stocked in sheet form. The individualunits are severed from the sheet, desirably immediately prior to thestacking operation. During the severing operation, notches 854 (FIG. 15)are formed in each unit in a pattern corresponding to the desiredpattern of notches for that unit. The notches formed in different unitswill be formed in different patterns. For example, a die 806 has a bladeportion 808 in the form of a rectangle so as to cut each unit fromadjacent units and has teeth 810 adapted to cut individual notches andsever individual branches 850 (FIG. 15). Teeth 810 are arranged to severthe branches in the pattern shown in FIG. 15. Thus, a tooth 810A isprovided to sever branch 850A, and similar teeth 810C and 810D areprovided to sever branches 850C and 850D. However, at a location 812corresponding to branch 850B, no tooth is provided and, hence, thisbranch is not severed. The dies used to cut other units from the tapewould have a different pattern of teeth. Other arrangements can be usedfor severing the units from the tape and concomitantly severing thebranches to be used. For example, water jet, laser or other cuttingdevices may be used to cut individual units from the tape and also tosever the branches. Similar arrangements can be used with the otherembodiments discussed above. For example, in those structures which havea pre-formed disconnection openings associated with the branches, thetool used to sever the unit from the sheet may have a projectionarranged to pass into such a disconnection opening and sever the branch.In a further alternative, the branch-severing operation can be performedwhile the various units remain connected in a sheet, desirablyimmediately before severing the individual units from the sheet. Thesheet optionally may be provided in the form of an elongated tape.

In yet another variant, the circuit panel 920 has an edge 924 withprojections 925 extending outwardly from such edge. A multi-branchedlead 938 has branches 950 extending outwardly onto the projections.Individual branches can be interrupted by severing one or more of theprojections as, for example, by severing projection 925A so as tointerrupt branch 950 a. This operation can be performed using a die orblade having recesses where projections are to remain attached. In thecompleted, stacked assembly, the remaining projections 925 can be bentout of the plane of the circuit panel, as shown in FIG. 19 at 925′, sothat the projections do not add substantially to the horizontal extentof the assembly.

Numerous variations and combinations of the features discussed above canbe utilized without departing from the present invention. For example,the various circuit panels may include additional features such asground or power planes or additional layers of traces. The traces andother conductive features of each panel can be placed on the second orchip-facing side of the panel rather than on the first side remote fromthe chip. For example, as shown in FIG. 20, the dielectric layer 1020has traces 1038 on the second or chip-facing side 1030 of dielectriclayer 1020. An additional solder mask layer 1002 may be provided overthe traces on side 1030 in addition to the solder mask layer 1076, whichalso serves as the heat transfer or thermal layer of the unit. Hereagain, the encapsulant 1033 within opening 1034 has a surface 1035 flushwith the first surface 1026 of the dielectric layer or recessed relativeto such surface, so that the first surface is substantially flat. In avariant, the solder mask layer 1076 on the first surface may be removedafter introduction of the encapsulant. In this instance, the dielectriclayer 1020 serves as the thermal or heat transfer layer of the unit andabuts the next lower chip in the stack. In a further variant, the soldermask layer 1002 on the second or chip-facing side of the dielectriclayer may be omitted or may be integrated with the adhesive layer 1068.Also, each unit can include more than one chip. The chips included inthe various units may be memory chips as, for example, DRAM, Flash, ROM,PROM or EEPROM chips. The invention also can be employed in packagingother chips as, for example, processors or application-specificintegrated circuits (ASICs). Also, the “select” terminals need notconvey a signal such as “chip select” commonly used in a memory array;any signal which is desirably routed to a specific chip or chips in astack can be conveyed. The adhesive layers, leads and panels may bearranged to permit movement of the unit terminals of each unit withrespect to the chip of that unit, so as to alleviate stresses due tothermal expansion. Also, the heat transfer layers may allow relativemovement of adjacent units. Further, the stacked assembly can includeone or more non-identical units in addition to the units substantiallyas described above. For example, the different units in the stack mayinclude different chips. In yet another variant, features discussedabove can be used in a structure where each unit has the chip disposedin an orientation, with the rear face of the chip abutting thedielectric layer of such unit and with the contact-bearing, front face,facing away from the dielectric layer. In such an embodiment, thecontacts can be connected to the traces by wire bonds or otherconductors. In such an embodiment, the front face of each chip, or alayer of encapsulant overlying the front face, may abut the dielectriclayer of the next adjacent unit.

A further variant in accordance with an aspect of the invention is shownin FIG. 21. FIG. 21 is similar to the variation shown in theabove-described FIG. 11. A multi-branched trace 1139 has a commonsection 1146 that is adapted for connection to a chip contact 1164. Thecommon section thus may have a bonding pad 1137 for use with a wire bondconnection to the chip contact or else may have a connection sectionwhich can be directly bonded to the chip contact as described earlier.The branches 1150 of the trace, when initially fabricated, do not extendin an unbroken, continuous path from the common section 1146 to thevarious select terminals 1122. Rather, each branch is initiallyfabricated with a gap 1151. The above-noted FIG. 11 illustrated the useof a short wire bond across the gap of one branch such that the gap isselectively closed for one, or more, of the branches. However, thesegaps can be selectively closed by other conductive elements. Forexample, solder may be selectively applied so as to bridge the gap ofone or more of the branches. In the embodiment of FIG. 21, each branch1150 of a multi-branched trace has an inner section 1121 connected tothe common section 1146 of the trace and an outer section 1123 connectedto the terminal 1122 associated with such branch. The inner sectiondefines a pad 1124 on one side of the gap 1151, whereas the outersection defines a pad 1125 on the opposite side of the gap, so that thegap is defined between the pads of the inner and outer sections of eachbranch. A solder mask layer covers the traces, but has an opening 1127associated with each branch encompassing the pads and gap of thatbranch. The solder mask also has an opening encompassing each terminal1122. To selectively connect the common section of the branch to oneselected terminal 1122 b, solder is applied on the pads of branch 1150 bso as to form a conductive bridge 1153 to span the gap 1151 between thepads of that branch. The solder can be applied as one or more masses onthe pads 1124 and 1125 of the selected branch as, for example, bydepositing a solder ball and, typically, flux, into the opening of thesolder mask encompassing the gap. Alternatively, the solder can beapplied as a mass of a solder paste, i.e., a dispersion of a solder inan organic carrier which dissipates when the paste is heated. Afterapplying the solder, the solder is heated to melt or ref lowing thesolder and form a bridging conductive element extending between the padsof the selected branch. The solder-applying and heating operation can beperformed in the same series of steps as used to deposit solder balls onthe terminals of the circuit panel and reflow the solder balls to jointhe panel to the next unit in the stack and form the vertical conductivebuses of the stack. Prior to application of the solder balls, all of theunits are identical to one another and can be handled and stocked asinterchangeable parts. The selective connections between the commonsections of the multi-branched traces and the terminals, which differfrom unit to unit, are formed in the same operations used for stackingthe units, and requires essentially no additional time or cost.

Desirably, the gaps in the branches are positioned in the peripheralregion of the circuit panel, outside of the region 1158 occupied by thechip (indicated in broken lines in FIG. 21), so that the solder bridge1153 extending across the gap will lie outside of the area occupied bythe chip. An encapsulant may optionally be applied over such a solderbridge. The solder bridge does not add to the overall height of thestacked assembly. As an alternative to solder, any other conductivematerials may be used such as, but not limited to, an organic conductiveadhesive.

In a further variant (FIG. 22) a multi-branched trace 1239 again has acommon section 1246 that is adapted for connection to a chip contact1264. The common section thus may have a bonding pad 1237 for use with awire bond connection to the chip contact or else may have a connectionsection which can be directly bonded to the chip contact as describedearlier. The branches 1250 of the trace, when initially fabricated, donot extend in an unbroken, continuous path from the common section 1246to the various select terminals 1222. Rather, each branch is initiallyfabricated with a pad or end 1221 disposed close to the select terminal1222 associated with such branch but out of contact with such selectterminal. Thus, each lead defines a gap 1251 between the pad 1221 andthe associated select terminal 1222. When the unit is manufactured, thepads 1222 are covered by a solder mask layer 1201. Similar to theearlier described embodiments, the select terminals 1222 are used tohold solder balls 1203, referred to herein as “bus solder balls”, forconnecting various units of a stacked package together and forming thevertical buses of the stack. Prior to application of the solder balls,each unit is selectively treated so as to remove a small piece of thesolder mask layer 1201 at the gap of a selected branch as, for example,by laser ablating the solder mask. For example, in FIG. 22 a smallportion of the solder mask has been removed so as to form an opening1253 in the solder mask encompassing pad at the end of branch 1250 b andmerging with the opening of the solder mask at the associated terminal1222 b. When the bus solder balls 1203 are applied on terminals 1203 andreflowed, the bus solder ball 1203 b on terminal 1222 b flows withinopening 1253 and thus flows onto the pad of branch 1250 b as well asonto the terminal 1222 b. The bus solder ball thus forms a bridgingconductive element integral with the bus solder ball connecting branch1250 b to terminal 1222 b. The other solder balls, associated with theother select terminals 1222, remain isolated from the other branchesbecause of the confining action of the solder mask layer during reflow.

This form of solder bridging can be accomplished by selectiveapplication of a solder flux (not shown) to the respective portion ofbranch 1250 and the gap to contact 1222 b. The solder flux enhanceswetting by the solder of the solder ball in the molten state, i.e.,during reflow. It should be noted that this “bridging” phenomenon isnormally regarded as undesirable and to be avoided in electrical circuitfabrication. Yet, and in accordance with an aspect of the invention,solder bridging of electrical connections can be used to selectivelyconnect signals as described herein. Indeed, other selective treatmentscan be used to selectively connect signals together. For example, a fluxor other material which promotes solder flow may be applied selectivelyin the gap between a branch and a terminal to provide solder flow acrossthe gap only at a selected branch or branches and thereby form bridgingconductive elements at only the selected branches. In this embodiment,the pads at the ends of the branches would not be covered by a soldermask when initially manufactured. In a further variant, the circuitpanel of each unit can be made with all of the branches having gapsarranged so that the pads at the ends of the branches would be wetted bythe bus solder balls on the associated terminals, and conductivebridging elements would be formed at all of the branches, if the unit isused in the as-manufactured condition. Before applying the solder balls,the units are selectively treated, as by selectively applying a soldermask or other material over the pads on some of the branches of eachmulti-branch trace, so that the applied material inhibits formation ofthe bridging conductive elements at some, but not all, of the branchesof each multi-branch trace. For example, spots of solder mask can beapplied by screen printing or dispensing a flowable dielectric andcuring the dielectric to form the solder mask where required.

The embodiment shown in FIG. 23 uses another arrangement to provideselective bridging. Here again, each unit includes a circuit panelhaving one or more multi-branched traces associated with the selectterminals of such unit. Each multi-branched trace 1339 has a commonsection 1346 that is adapted for connection to a chip contact 1364 asdescribed earlier. The branches 1350 terminate in respective pads 1353a, 1353 b, etc. and, when initially fabricated, do not extend in anunbroken, continuous path from the common section 1346 to the variousselect terminals 1322. In particular, each of the pads of branch 1350 isseparated from the associated terminal 1322 across a gap 1351. In thisexample the terminals of branch 1350 and the select terminals 1322 lieoutside of the region 1358 occupied by the chip (indicated in brokenlines in FIG. 23) and are along the periphery of the circuit panel.Similar to the earlier described embodiments, the select terminals 1322are used to hold bus solder balls (not shown in FIG. 23) for connectingthe corresponding terminals of the various units of a stacked packagetogether and forming the vertical buses.

In addition, each of the terminals 1353 also provides support for asolder ball referred to herein as an “auxiliary” solder ball. However,the auxiliary solder balls for use on terminals 1353 are selectivelyapplied to pads 1353 only where bridging conductive elements are to beformed. Thus one or more, of the select terminals 1322 is electricallycoupled to the pad 1353 of the associated branch 1350 upon reflow, e.g.,in forming the stacked package. In other words, the adjacent bus andmain solder balls are joined together upon reflow, thus, selectivelybridging one, or more, terminals 1322 to multi-branched trace 1339. Assuch the distance 1354 between pads 1353 and terminals 1322 is selectedsuch that upon reflow, an auxiliary solder ball (if present) will bridgeto an adjacent bus solder ball.

This is further illustrated in FIG. 24. A stacked assembly 1375 issimilar to the other stacks described above and, e.g., includes a numberof circuit panels, or units, 1382 arranged in a vertical stack andcoupled to each other via conductive elements as represented bus solderballs 1386. As shown in FIG. 24 a number of auxiliary solder balls 1380,are applied to one, or more, of pads 1353. Upon reflow, bus solder balls1386 form a conductive mass to couple corresponding terminals of thevarious circuit panels together. Where the auxiliary solder balls 1380are present, they merge with the bus solder balls to form conductiveelements integral with the bus solder balls which selectively bridge thegaps 1351 between pads 1353 and terminals 1322. This is furtherillustrated in FIG. 25, where solder masses, after reflow, arerepresented by various diagonal shading and, in particular, solder mass1396 illustrates a selective bridging between a terminals 1322 and a pad1353.

As described above, a stacked assembly comprises a plurality of units,each unit desirably including at least one semiconductor chip arrangedon at least one circuit panel. In this stacked assembly, vertical busesand traces on the circuit panels of the individual units convey signalsto the various chips of the stacked assembly. For example, in the caseof a stacked assembly comprising a vertical array of memory chips, thevertical buses convey signals such as data, address, and control as wellas one or more supply voltages and ground paths. An overall signal pathfor a particular signal includes, e.g., the traces on the circuit board,the vertical busses of a stacked package and the corresponding traces oneach of the circuit panels of the stacked package. Such a path may havean appreciable signal propagation time. Consequently, signal reflectionfrom an end of the signal path may become a concern. Signal reflectionscan arise, for example, in traces ending in a stacked package and at theupper ends of the vertical buses. Signal reflection causes signaldistortion and noise, which may lead to errors in operation of thecircuit and/or limitations on the speed of operation of the circuit.

Therefore, and in accordance with another aspect of the invention, astacked assembly includes one, or more, terminating elements, preferablyelectrically connected to the vertical buses or traces at or near thetop of the stacked assembly for reducing signal reflection on one, ormore, traces or buses of the stacked assembly. As used herein, the topof the stacked assembly is that region opposite the bottom of thestacked assembly, whereas the bottom of the stacked assembly is thatregion of the assembly which will lie closest to the circuit board orother substrate which receives the stacked assembly when the stackedassembly is mounted on such substrate. Although, the terminationelements are preferably at a top of a stacked assembly, this is notrequired.

A signal line which simply ends at a point unconnected to any otherelectrical component presents essentially infinite impedance to signalspassing along the line and reaching the end point. The term “terminationelement” as used in this disclosure refers to an element which providesa predetermined electrical characteristic other than a substantiallyinfinite impedance. An illustrative termination element 1110 is shown inFIG. 26. Termination element 1110 is a network which includes a pull-upelement, as represented by resistor 1109, and a pull-down element, asrepresented by resistor 1108, arranged between a voltage, V, and asignal ground, G. A conductive element 1105, such as a trace or busterminated by element 1110, applies a signal to a signal node 1107 oftermination network 1110. As known in the art, the selection of actualimpedance values for termination network 1110 depends on the particularcircuit configuration and desired operating characteristics. Further,other types of termination networks may be used such as, but not limitedto, resistor-capacitor (RC) terminations, resistor capacitor diode (RCD)terminations, etc. In addition, such terminations may include only apull-up element connected between the signal path to be terminated and asource of constant voltage or a pull-down element connected between thesignal path to be terminated and ground. Finally, a series terminationelement may also be incorporated in addition to, or instead of, thepull-up and/or pull-down elements.

As shown in FIG. 27, a stacked assembly 1175 includes according to oneembodiment of the invention e.g., includes a plurality of units 1190,referred to herein as the “operational” units, each including a circuitpanel 1182 and a semiconductor chip 1181 mounted to the circuit panel.Each operational unit has terminals 1192 and traces 1191 connecting theterminals to contacts of the semiconductor chip. Here again, theoperational units are arranged in a vertical stack and coupled to eachother via conductive elements as represented by solder balls 1183connecting corresponding terminals of the various units and formingvertical buses. A fifth unit 1193, referred to herein as a “terminationunit” includes a circuit panel 1186 having mounted thereon an integratedpassive chip or “IPOC” (Integrated Passives On a Chip) 1180 connected toterminals 1111 by traces on panel 1186.

Terminals 1111 of termination unit 1193 are arranged in a patterncorresponding to the pattern of terminals 1192 on the operational units1190, and terminals 1111 are connected to the various vertical buses ofthe stack. The ground and power buses of the stack provide ground andpower potentials to the termination elements 1110 included in the IPOC1180 of termination unit 1193. For example, as seen in FIG. 28, terminal1111A of the termination unit connects to a ground bus, terminal 1111Bis connected to a signal bus and terminal 1111C is connected to a powervoltage vertical bus. Terminals 1111A and 1111C are coupled via traces1116 and 1118, respectively to the ground and power nodes of a pull-up,pull-down network or termination element 1110 within IPOC 1180. Terminal1111B is coupled to the signal node of the termination element throughtrace 1117, so that the termination element provides termination for thesignal bus connected to terminal 1111B. Typically, IPOC 1180 includes alarge number of termination elements, which may be of any of the typesdescribed above. It is not necessary to provide separate ground or powervoltage connections for all of the individual termination elements; theground nodes of numerous termination elements can be connected to acommon terminal 1111, and the power voltage nodes of numeroustermination elements also may be connected to a common terminal 1111. Asin the embodiments discussed above, stacked assembly 1175 is mounted toa circuit board 1184 (FIG. 27). In operation, the termination elementsprovide controlled impedances at the upper ends of the vertical buses,and thus limit signal reflections.

Other arrangements are possible. For example, the IPOC may be providedwith contacts in a pattern matching the pattern of terminals on theoperational units, so that contacts of the IPOC may be attached directlyto the tops of the vertical buses. In this arrangement, the terminationunit may consist solely of the IPOC, with no separate circuit panel.Moreover, it is not essential to provide termination elements connectedto all of the vertical buses. For example, in some memory chips the databuses may operate at considerably higher frequencies than buses used toconvey addresses or commands, and hence signal reflections in the databuses may be more significant than signal reflections in the address orcommand buses. In this case, the termination unit may providetermination elements associated only with the data buses. In otherarrangements, the termination elements may include discrete elementsmounted to the circuit panel 1186, or even integrated within the circuitpanel.

Turning now to FIG. 29, another variation in accordance with anotheraspect of the invention is shown. In this illustrative embodimentpassive components are used as vertical conductors in place of one, ormore, solder balls for coupling units of a stacked assembly together.The stacked assembly of FIG. 29 is similar to the other stacks describedabove and, e.g., includes a number of circuit panels 1486 arranged in avertical stack and coupled to each other via conductive elements asrepresented by solder balls 1483. In addition, the stacked assemblyincludes one, or more, passive components, coupled between these circuitpanels. This is illustratively shown in FIG. 29 by passive components1401, 1402, 1403, 1404 and 1405. Preferably, each passive component issmall enough to span the gap 1495 between adjacent circuit panels. Forexample, a passive component such as a resistor, capacitor, inductor orthe like 1401 may have a small housing 1420 with metallic end caps 1421at its top and bottom ends. The end caps may be connected to thecorresponding terminals 1423 of two adjacent units in the stack by abonding material such as solder which coats the end caps but which doesnot bridge between the end caps and hence does not short-circuit thepassive element within the housing. In manufacture of such anarrangement, the passive elements may be pre-coated with the bondingmaterial so that they can be applied in manner similar to solder balls.The exterior of housing 1420 may have a polymeric or other surface whichis not wettable by the bonding material and hence resists bridging bythe bonding material.

The passive elements in FIG. 29 are connected in series with one anotherand hence form one of the vertical buses of the stack. Any number ofother variations are possible. In one example (FIG. 30) a passiveelement 1471 connected may be connected between a first terminal 1472 ofa first unit 1477 in the stack and a first terminal 1473 of an adjacentsecond unit 1478. The first terminal of the second unit in turn may beconnected by a trace 1479 on the second unit to a second terminal 1474of the second unit, which in turn is connected by a solder ball 1475 toa second terminal 1476 of the first unit. In such an arrangement, thepassive element, although physically connected between adjacent units,is electrically connected between terminals of the first unit and henceis incorporated in the internal circuitry of the first unit rather thanforming part of a vertical bus. In a further variant, solder ball 1475may be replaced by a further passive element (not shown) so that twopassive elements are connected in series in the internal circuit of thefirst unit 1477.

In a further embodiment (FIG. 31), a passive element 1451 is connectedbetween a signal-carrying terminal 1452 of the topmost operative unit ofthe stack circuit and a metallic shield 1453 overlying the top of thestack. Shield 1453 has a side wall 1454 extending vertically to thebottom of the stack. When the stack is mounted to a circuit board 1484,the shield is electrically connected to ground. The passive component isthus connected between the top of a vertical signal bus 1455 and aground potential applied through the shield. In such an arrangement,passive component 1451 serves as a terminating element. For example,passive component 1452 may be a simple resistor to provide a pull-downtermination at the top of the signal bus. In the embodiment of FIG. 31,one or more vertical ground buses are connected by conductive elementssuch as solder balls 1483 to the shield. This arrangement illustratesthat the ground or power connections of termination elements to thecircuit board can be made by connections other than the vertical busesof the stacked assembly.

Stacked package assemblies may include one, or more, components, whichgenerate or process signals at high frequencies as, for example, aprocessing chip, a high-speed memory, a radio frequency power amplifieror receiver. These components may be a source of electromagneticradiation that can interfere with the operations of other devices orcircuits in the vicinity of the radiating components. Also, componentsof a stacked package assembly may be susceptible to electro-magneticinterference generated externally to the stacked package and impingingthereon.

A stacked package assembly according to a further embodiment of theinvention incorporates a Faraday cage for electromagnetic shielding. Anoperative unit 1501 (FIG. 32) used in this embodiment includes a circuitpanel 1519 having an array of terminals 1524, referred to herein as“shielding terminals” placed along and around the peripheral edges 1529of circuit panel 1519. Terminals 1524 are shown in broken line form. Asdescribed below, the shielding terminals 1524 will be used to form theFaraday cage. Adjacent shielding terminals are spaced apart from oneanother by a center-to-center distance D_(F), which desirably is uniformaround the entire periphery of the circuit panel. A second array ofterminals 1525, referred to herein as “signal terminals” is locatedfurther within circuit panel 1519. This second array of terminals 1525is arranged inside the array of shielding terminals. The signalterminals may include the terminals required for operation of the unitsin the stacked assembly, and may convey various electrical signals, suchas those described above, including, for example, power, address, data,etc., to and from the chip, or chips. The signal terminals optionallymay include chip select terminals as discussed above. The signalterminals 1525 are depicted as being disposed near the periphery edgesof panel 1526, but can be disposed anywhere inside the array ofshielding terminals 1524. A chip, or chips, 1527 or other operationalelectronic components may also be mounted to circuit panel 1519 within aregion inside the array of shielding terminals 1524. Traces coupling thechips, or chips, to various ones of the signal terminals are not shownfor simplicity.

As shown in FIG. 33, a stacked assembly in accordance with thisembodiments includes a plurality of units 1501 as described above withreference to FIG. 32, each incorporating a circuit panel 1519 with oneor more operational components such as one or more semiconductor chips.These units 1501 are referred to herein as the operative units of theassembly. The stacked assembly also includes a topmost unit 1503,referred to herein as a “shielding unit.” The shielding unit includes anelectrically conductive plane element 1505 and terminals 1507 in apattern corresponding to the pattern of shielding terminals 1524 on thecircuit panels of the operational unit. The shielding unit may consistsolely of a conductive plane 1505 such as a metallic element with asolder mask 1509 to define portions of the element as terminals.Alternatively, the shielding unit may include additional elements suchas a circuit panel (not shown) defining traces and terminalscorresponding to the signal terminals of the operative units, as well asa chip or other electronic components connected to the traces.Conductive elements such as solder balls 1534, interconnectcorresponding shielding terminals 1524 of the operational units with oneanother and with corresponding terminals 1507 of the shielding unit 1503so as to form a plurality of vertical shielding buses 1540. Thehorizontal spacing between the shielding solder balls is D_(F) (as shownin FIG. 32). Corresponding signal terminals 1525 (FIG. 32) of theoperative units 1501 are also connected to one another by conductiveelements (not shown) so as to form additional vertical buses. In use,the shielding solder balls 1534 of the lowest unit 1501 a in the stackalso make contact with ground contact pads 1585 of circuit board 1584.The contact pads 1585 of circuit board 1584 provide a conductive path toan electrical ground (not shown), i.e., a circuit ground of circuitboard 1584. The vertical shielding buses 1540 and the conductive plane1505 of the shielding unit cooperatively define a Faraday cage whichlimits propagation of electromagnetic signals between the electroniccomponents of the operative units 1501 and the surroundings outside ofthe stacked assembly.

The efficacy of the cage in blocking electromagnetic radiation isrelated to the wavelength of the radiation and to the spacing ordistance between the vertical shielding buses 1540 constituting theconductors of the Faraday cage. Generally, a Faraday cage will blockthose electromagnetic frequencies having a wavelength approximatelyequal to, or greater than, the distance between adjacent conductors ofthe cage. A Faraday cage will fail to provide a shield above some cutofffrequency, where the distance between adjacent conductors issubstantially greater than the wavelength of the emitted electromagneticradiation. The distance, D_(F), between shielding terminals 1524 isselected in accordance with the desired shielding characteristics of theFaraday cage. Preferably, D_(F) is selected to provide shielding up toand above a maximum shielding frequency which in turn is selected basedon a principal electrical frequency associated with the electroniccomponents mounted in the operative units 1501 of the stacked assembly.In the case of a digital chip having internal components adapted tooperate in synchronism with a clock signal, the principal frequency canbe taken as the maximum operating clock frequency of the chip. In thecase of analog RF components such as an RF receiver or transmitter, theprincipal frequency can be taken as the maximum radio frequency used inoperation of the components. Desirably, D_(F) is selected to provideeffective shielding up to a maximum shielding frequency which is two ormore times the principal frequency. As a first approximation, thedistance between conductors can be taken as equal to thecenter-to-center distance D_(F) between adjacent shielding terminalsminus the diameter D_(B) of an individual solder ball prior to reflowand accordingly D_(F) can be selected to provide a desired maximumshielding frequency. Using this approximation, the value (D_(F)−D_(B))is selected to be less than or equal to the wavelength corresponding tothe desired maximum shielding frequency.

As shown in FIG. 34, a circuit panel 1619 used in operative units of astacked assembly according to a further embodiment has terminals 1627that are placed along and around the peripheral edges 1629 of thecircuit panel. Terminals 1627 include shielding terminals 1624,indicated in broken line form, and signal terminals 1625, indicated insolid line form, the signal terminals being interspersed with theshielding terminals. Between every pair of shielding terminals 1624 maybe one or more signal terminals 1625. FIG. 34 depicts a signal terminal1625 between every pair of shielding terminals 1624. However, it is notrequired that one or more signal terminals exist between every pair ofshielding terminals. Traces coupling leads of the chips, or chips, tovarious ones of the terminals are not shown for simplicity. In the sameway as discussed above with reference to FIG. 33, one or more operativeunits of the type shown in FIG. 34 are assembled with a shielding unit(not shown) having a conductive plane and shielding terminals in apattern corresponding to the pattern of shielding terminals 1624. Hereagain, corresponding terminals on the various units are connected to oneanother to form vertical buses; once again, the buses incorporating theshielding terminals are used to form the Faraday cage. In thisembodiment as well, the center-to-center distance D_(F) between adjacentshielding terminals is selected as described above in accordance withthe desired shielding characteristics of the Faraday cage.

The Faraday cage can be used to shielding other devices or circuits fromthe electromagnetic radiation of a stacked assembly, or to shield thecomponents of a stacked assembly from electromagnetic radiationimpinging on the assembly from the outside. The Faraday cage can beformed economically, and adds little to the overall size of the stackedassembly. The vertical shielding buses typically are connected to groundby the circuit board, and hence connect the conductive plane of theshielding unit to ground. Some or all of the shielding terminals in theoperative units can be provided with traces connecting these terminalsto the electronic devices in the operative units, so that the verticalshielding buses also serve as ground connections for the electronicdevices. Also, although the Faraday cage and the associated conductiveplane at the top of the assembly are almost always connected to groundpotential, this is not essential; the cage and conductive plane can beconnected, for example, to another a power supply or other constantvoltage source available on the circuit board. Further, the verticalbuses forming the Faraday cage can be used without a ground plane orother conductive plane incorporated in the assembly. For example, insome applications it may not be necessary to provide shielding againstelectromagnetic radiation at the top of the assembly. Alternatively,other elements such as an overlying circuit board or heat shield mayprovide shielding at the top of the assembly. If the conductive plane isomitted, the vertical buses included in the Faraday cage desirably areelectrically interconnected with one another by other elements of thestacked assembly or by elements in the circuit board to which theassembly is mounted. Similarly, it is not always essential to providethe vertical shielding buses around the entire periphery of the stack.For example, the embodiment of FIG. 31 has a separate shield 1454extending along one side. In such a structure, the vertical shieldingbuses may be omitted on that side of the assembly.

In the embodiments discussed above, the conductive elements connectingthe various units to one another and forming the vertical conductors areconventional solder balls. Other conductive elements may be employedinstead. For example, so-called “solid core solder balls” can be used.Solid core solder balls include cores formed from a material having arelatively high melting point and a solder having a melting temperaturelower than the melting temperature of the core. Still other conductiveelements can be formed from masses of a conductive polymer composition.Further, although the conductors extending between units in a stackedassembly are described above as “vertical”, these conductors need notextend exactly perpendicular to the planes of the circuit panels; thevertical conductors or buses may be sloped so that they extendhorizontally as well as vertically.

As these and other variations and combinations of the features set forthabove can be utilized, the foregoing description of the preferredembodiment should be taken by way of illustration rather than bylimitation of the invention.

1. A method of making semiconductor chip assembly comprising the stepsof: (a) stacking a plurality of units each including at least onesemiconductor chip having at least one chip select contact and aplurality of other contacts and a circuit panel having a plurality ofchip select terminals, a plurality of other terminals, and tracesextending on or in the panel connected to said terminals, said traces ofeach panel including a plurality of traces connecting said othercontacts with said other terminals, at least one trace of each saidpanel being a multi-branched trace associated with plurality of saidchip select terminals on such panel, each such multi-branched traceincluding a common section and a plurality of branches, each one of theplurality of branches being associated with one said chip selectterminals, each one of said branches defining a gap intervening betweenthe common section of the trace incorporating such branch and theterminal associated with such branch; (b) selectively connecting abridging conductive element across the gap defined by at least onebranch, but less than all branches, of each such multi-branched trace,whereby the common section of each multi-branched trace is connected toless than all of the chip select terminals associated with the branchesof such multi-branched trace; and (c) interconnecting terminals ofdifferent units to one another to form vertical buses, said selectivelyconnecting and interconnecting steps being performed so that the chipselect contacts of chips in different units are connected to differentones of said vertical buses.
 2. A method as claimed in claim 1 whereinsaid circuit panels, prior to said selectively connecting step, areidentical to one another.
 3. A method as claimed in claim 2 furthercomprising the step of handling and stocking said units as mutuallyinterchangeable parts prior to said selectively connecting step.
 4. Amethod as claimed in claim 2 wherein said stacking step includesaligning corresponding terminals of circuit panels in different unitswith one another.
 5. A method as claimed in claim 1 wherein saidselectively connecting step is performed so that the common section ofeach said multi-branched trace is connected to only one select terminalof the circuit panel bearing such trace.
 6. A method as claimed in claim1 further comprising the step of forming said units by connecting chipsto circuit panels, wherein said selectively connecting step is performedafter said step of forming said units.
 7. A method as claimed in claim 1wherein said selectively connecting step is performed in the samefacility as said stacking step.
 8. A method as claimed in claim 1wherein selectively connecting step includes applying wire bonds acrossat least some of said gaps.
 9. A method as claimed in claim 11 whereinsaid selectively connecting step includes engaging a mass of materialformed integrally with a wire between a tool and pads defining the gapand applying energy to the mass and pads while squeezing the massbetween said tool and said pads, and then disconnecting the mass fromthe wire so as to leave said mass connected to the pads and bridging thegap.
 10. A method as claimed in claim 1 wherein said selectivelyconnecting step includes forming masses of an electrically conductivebonding material across at least some of said gaps.
 11. A method asclaimed in claim 10, wherein said selectively connecting step includesthe step of forming solder bridges across the at least some of saidgaps.
 12. A method as claimed in claim 11, wherein said interconnectingstep includes connecting bus solder masses between terminals of adjacentunits, and wherein said step of forming said solder bridges includesforming said solder bridges integral with said bus solder masses.
 13. Amethod as claimed in claim 12 wherein said branched traces define padsadjacent said select terminals but not connected thereto, and said stepof forming said solder bridges integral with said solder masses includesapplying auxiliary solder masses only on the pads of branches where saidbridging conductive elements are to be formed so that said auxiliarysolder masses merge with said bus solder masses.
 14. A method as claimedin claim 12 wherein said branched traces define pads adjacent saidselect terminals but not connected thereto, and said step of formingsaid solder bridges integral with said solder masses includesselectively treating said circuit panels adjacent said pads and selectterminals so that said bus solder masses flow to only the pads ofbranches where said bridging conductive elements are to be formed.
 15. Amethod as claimed in claim 11, wherein said steps of selectivelyconnecting and interconnecting are performed during a common reflowprocess.
 16. A method as claimed in claim 1, wherein said steps ofselectively connecting and interconnecting are performed atsubstantially the same time.
 17. A method of making connections betweenconductive elements on a circuit panel comprising the steps: (a)squeezing a mass of an electrically conductive material between a tooland a pair of electrically conductive elements exposed at a top surfaceof the circuit panel and defining a gap therebetween while applyingsonic energy to said mass so as to bond said mass to both of saidconductive elements; and then (b) retracting said tool so as to leavesaid mass bridging the gap between said conductive elements.
 18. Amethod as claimed in claim 17 wherein said mass is formed integrallywith a wire, the method further comprising severing the wire from themass after said squeezing step.
 19. A method as claimed in claim 18wherein said mass is a ball having a diameter and said gap has a widthless than the diameter of the ball.
 20. A method as claimed in claim 19wherein said gap has a width of 40 μm or less.
 21. A method as claimedin claim 18 wherein said mass and said wire include material selectedfrom the group consisting of gold, gold alloys, aluminum and aluminumalloys.
 22. A method as claimed in claim 18 wherein said conductiveelements are pads formed integrally with trace portions, whereby saidmass connects said trace portions to form a continuous trace.
 23. Amethod as claimed in claim 17 wherein said squeezing step includessupporting a bottom surface of said circuit panel opposite from said topsurface on a support.